Graphics, sound and multimedia • Re: Raspberry Pi with DSI86 for DSI to eDP bridge

Keep in mind that you will only be able to make use of DSI86 single channel DSI input (=4-lanes) as the DSI interfaces on the Pi5 are individual peripherals, means you can't connect them for dual channel DSI applications. This will limit the max resolution which you can use the DSI86 with.
Once calculated it if one can achieve 2560x1440 from 4-lane DSI but wasn't convinced to spend money on trying it (and if a CM4 is able to output this resolution).

The limit on CM4 is nominally 1Gbit/s/lane, ie 4 Gbit/s total on 4 lanes. You're on an integer divider from 3GHz, so the next would be 1.5GHz, which I couldn't say if it would work or not - 50% is a heck of an overclock.
Looking at the JDI LT070ME050000 driver, that has a pixel clock of 155473kHz, so at 24bpp that is 3.73Gbits/s for 1200x1920@60.
2560x1440@60 is going to be up around 5.5Gbit/s, so if the hardware will overclock to 1.5Gbit/s/lane you may stand a chance. It may require a core clock bump to be able to feed pixels to the DSI block at a sufficient rate.

AFIK the RP1 will not be able to output such high resolutions on single channel (4-lane) DSI --> it would not be possible to drive my 13.3in TFT's.

I think njh quoted a pixel clock limit on RP1's DSI, but i can't remember if that was 200MPix/s or 250MPix/s.

As for Raspberry Pi 5 DSI in particular: 1.5Gbps is the maximum MIPI D-PHY bit rate per lane. There are 4 data lanes so with appropriate hardware the max total bit rate is 6Gbps.

RP1's video output supports most RGB framebuffer formats and resolutions. But it's strictly limited to < 200Mpix/second, including blanking intervals. That's just fast enough for 1920x1200@60Hz. 24-bit depth should be feasible (at about 4Gbps over 4 lanes).

Statistics: Posted by aBUGSworstnightmare — Tue May 07, 2024 8:52 am